On Sat, Nov 02, 2019 at 10:57:47AM +0100, Paolo Bonzini wrote:
> On 01/11/19 23:41, Suthikulpanit, Suravee wrote:
> > + /*
> > + * AMD SVM AVIC accelerates EOI write and does not trap.
> > + * This cause in-kernel PIT re-inject mode to fail
> > + * since it checks ps->irq_ack before kvm_set_irq()
> > + * and relies on the ack notifier to timely queue
> > + * the pt->worker work iterm and reinject the missed tick.
> > + * So, deactivate APICv when PIT is in reinject mode.
> > + */
> > if (reinject) {
> > + kvm_request_apicv_update(kvm, false, APICV_DEACT_BIT_PIT_REINJ);
> > /* The initial state is preserved while ps->reinject == 0. */
> > kvm_pit_reset_reinject(pit);
> > kvm_register_irq_ack_notifier(kvm, &ps->irq_ack_notifier);
> > kvm_register_irq_mask_notifier(kvm, 0, &pit->mask_notifier);
> > } else {
> > + kvm_request_apicv_update(kvm, true, APICV_DEACT_BIT_PIT_REINJ);
> > kvm_unregister_irq_ack_notifier(kvm, &ps->irq_ack_notifier);
> > kvm_unregister_irq_mask_notifier(kvm, 0, &pit->mask_notifier);
>
> This is not too nice for Intel which does support (through the EOI exit
> mask) APICv even if PIT reinjection active.
Hmm, it's tempting to just make svm_load_eoi_exitmap() disable AVIC when
given a non-empty eoi_exit_bitmap, and enable it back on a clear
eoi_exit_bitmap. This may remove the need to add special treatment to
PIT etc.
Thanks,
Roman.
