Paolo,
Thanks for quick response.
On 11/2/19 4:57 AM, Paolo Bonzini wrote:
> On 01/11/19 23:41, Suthikulpanit, Suravee wrote:
>> + /*
>> + * AMD SVM AVIC accelerates EOI write and does not trap.
>> + * This cause in-kernel PIT re-inject mode to fail
>> + * since it checks ps->irq_ack before kvm_set_irq()
>> + * and relies on the ack notifier to timely queue
>> + * the pt->worker work iterm and reinject the missed tick.
>> + * So, deactivate APICv when PIT is in reinject mode.
>> + */
>> if (reinject) {
>> + kvm_request_apicv_update(kvm, false, APICV_DEACT_BIT_PIT_REINJ);
>> /* The initial state is preserved while ps->reinject == 0. */
>> kvm_pit_reset_reinject(pit);
>> kvm_register_irq_ack_notifier(kvm, &ps->irq_ack_notifier);
>> kvm_register_irq_mask_notifier(kvm, 0, &pit->mask_notifier);
>> } else {
>> + kvm_request_apicv_update(kvm, true, APICV_DEACT_BIT_PIT_REINJ);
>> kvm_unregister_irq_ack_notifier(kvm, &ps->irq_ack_notifier);
>> kvm_unregister_irq_mask_notifier(kvm, 0, &pit->mask_notifier);
>
> This is not too nice for Intel which does support (through the EOI exit
> mask) APICv even if PIT reinjection active.
I see you point.
> We can work around it by adding a global mask of inhibit reasons that
> apply to the vendor, and initializing it as soon as possible in vmx.c/svm.c.
>
> Then kvm_request_apicv_update can ignore reasons that the vendor doesn't
> care about.
>
> Paolo
>
What about we enhance the pre_update_apivc_exec_ctrl() to also return
success/fail. In here, the vendor specific code can decide to update
APICv state or not.
Thanks,
Suravee
