On Thu, Oct 24, 2019 at 08:34:21AM -0400, Liu Yi L wrote: > Shared virtual address (SVA), a.k.a, Shared virtual memory (SVM) on Intel > platforms allow address space sharing between device DMA and applications. > SVA can reduce programming complexity and enhance security. > This series is intended to expose SVA capability to VMs. i.e. shared guest > application address space with passthru devices. The whole SVA virtualization > requires QEMU/VFIO/IOMMU changes. This series includes the QEMU changes, for > VFIO and IOMMU changes, they are in separate series (listed in the "Related > series"). > > The high-level architecture for SVA virtualization is as below: > > .-------------. .---------------------------. > | vIOMMU | | Guest process CR3, FL only| > | | '---------------------------' > .----------------/ > | PASID Entry |--- PASID cache flush - > '-------------' | > | | V > | | CR3 in GPA > '-------------' > Guest > ------| Shadow |--------------------------|-------- > v v v > Host > .-------------. .----------------------. > | pIOMMU | | Bind FL for GVA-GPA | > | | '----------------------' > .----------------/ | > | PASID Entry | V (Nested xlate) > '----------------\.------------------------------. > | | |SL for GPA-HPA, default domain| > | | '------------------------------' > '-------------' > Where: > - FL = First level/stage one page tables > - SL = Second level/stage two page tables Yi, Would you mind to always mention what tests you have been done with the patchset in the cover letter? It'll be fine to say that you're running this against FPGAs so no one could really retest it, but still it would be good to know that as well. It'll even be better to mention that which part of the series is totally untested if you are aware of. Thanks, -- Peter Xu
