On Wed, Oct 9, 2019 at 12:02 AM Paolo Bonzini <pbonzini@xxxxxxxxxx> wrote: > > On 09/10/19 02:41, Aaron Lewis wrote: > > - /* > > - * The only supported bit as of Skylake is bit 8, but > > - * it is not supported on KVM. > > - */ > > - if (data != 0) > > - return 1; > > This comment is actually not true anymore; Intel supports PT (bit 8) on > Cascade Lake, so it could be changed to something like > > /* > * We do support PT (bit 8) if kvm_x86_ops->pt_supported(), but > * guests will have to configure it using WRMSR rather than > * XSAVES. > */ > > Paolo Isn't it necessary for the host to set IA32_XSS to a superset of the guest IA32_XSS for proper host-level context-switching? arch/x86/kernel/fpu/xstate.c has this comment: * Note that we do not currently set any bits on IA32_XSS so * 'XCR0 | IA32_XSS == XCR0' for now.
