On 03/10/19 19:20, Jim Mattson wrote: > You've truncated the list I originally provided, so I think this need > only go to MSR_ARCH_PERFMON_PERFCTR0 + 17. Otherwise, we could lose > some valuable MSRs. This is v2, so it was meant to replace the patch that truncates the list. But I can include the other one too, perhaps even ask the x86 maintainers about decreasing INTEL_PMC_MAX_GENERIC to 18. >> + if (msrs_to_save[i] - MSR_ARCH_PERFMON_PERFCTR0 >= >> + min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) > Why involve INTEL_PMC_MAX_GENERIC here? It's not really necessary, but I wanted to imitate how intel_pmu_refresh initializes pmu->nr_arch_gp_counters. Paolo >> + continue; >> + break; >> + case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL0 + 31: > Same as the two comments above. >> + if (msrs_to_save[i] - MSR_ARCH_PERFMON_EVENTSEL0 >= >> + min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) >> + continue;
