> From: Peter Xu [mailto:peterx@xxxxxxxxxx] > Sent: Wednesday, September 25, 2019 2:57 PM > > On Wed, Sep 25, 2019 at 10:48:32AM +0800, Lu Baolu wrote: > > Hi Kevin, > > > > On 9/24/19 3:00 PM, Tian, Kevin wrote: > > > > > > '-----------' > > > > > > '-----------' > > > > > > > > > > > > This patch series only aims to achieve the first goal, a.k.a using > > > first goal? then what are other goals? I didn't spot such information. > > > > > > > The overall goal is to use IOMMU nested mode to avoid shadow page > table > > and VMEXIT when map an gIOVA. This includes below 4 steps (maybe not > > accurate, but you could get the point.) > > > > 1) GIOVA mappings over 1st-level page table; > > 2) binding vIOMMU 1st level page table to the pIOMMU; > > 3) using pIOMMU second level for GPA->HPA translation; > > 4) enable nested (a.k.a. dual stage) translation in host. > > > > This patch set aims to achieve 1). > > Would it make sense to use 1st level even for bare-metal to replace > the 2nd level? > > What I'm thinking is the DPDK apps - they have MMU page table already > there for the huge pages, then if they can use 1st level as the > default device page table then it even does not need to map, because > it can simply bind the process root page table pointer to the 1st > level page root pointer of the device contexts that it uses. > Then you need bear with possible page faults from using CPU page table, while most devices don't support it today. Thanks Kevin
