On Tue, Sep 17, 2019 at 04:52:55PM +0800, Yang Weijiang wrote: > EPT-Based Sub-Page write Protection(SPP)is a HW capability which allows > Virtual Machine Monitor(VMM) to specify write-permission for guest > physical memory at a sub-page(128 byte) granularity. When this > capability is enabled, the CPU enforces write-access check for sub-pages > within a 4KB page. > > The feature is targeted to provide fine-grained memory protection for > usages such as device virtualization, memory check-point and VM > introspection etc. > > SPP is active when the "sub-page write protection" (bit 23) is 1 in > Secondary VM-Execution Controls. The feature is backed with a Sub-Page > Permission Table(SPPT), SPPT is referenced via a 64-bit control field > called Sub-Page Permission Table Pointer (SPPTP) which contains a > 4K-aligned physical address. > > To enable SPP for certain physical page, the gfn should be first mapped > to a 4KB entry, then set bit 61 of the corresponding EPT leaf entry. > While HW walks EPT, if bit 61 is set, it traverses SPPT with the guset > physical address to find out the sub-page permissions at the leaf entry. > If the corresponding bit is set, write to sub-page is permitted, > otherwise, SPP induced EPT violation is generated. > > This patch serial passed SPP function test and selftest on Ice-Lake platform. > > Please refer to the SPP introduction document in this patch set and > Intel SDM for details: > > Intel SDM: > https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf > > SPP selftest patch: > https://lkml.org/lkml/2019/6/18/1197 > > Previous patch: > https://lkml.org/lkml/2019/8/14/97 I saw the patches as part of the introspection patch-set. Are you all working together on this? Would it be possible for some of the bitdefender folks who depend on this to provide Tested-by adn could they also take the time to review this patch-set? Thanks.
