On Wed, Aug 7, 2019 at 4:54 PM Sean Christopherson <sean.j.christopherson@xxxxxxxxx> wrote: > > On Wed, Aug 07, 2019 at 02:52:19PM -0700, Jintack Lim wrote: > > Hi, > > > > I'm just wondering what's the reason why we use the preemption timer > > instead of emulating VM's timer using hrtimer in software? Is there > > anything the the preemption timer can do that can't be done with > > hrtimer? > > > > I guess the x86 architecture provides the preemption timer for *some* > > reason, but I'm not sure what they are. > > Assuming you're referring to Intel/VMX's preemption timer, programming > the preemption timer and servicing its VM-Exits both have lower overhead > than going through hrtimer. Yes, I was referring to the VMX preemption timer. Thanks for the pointer. It's very nice to know! Thanks, Jintack > > commit ce7a058a2117f0bca2f42f2870a97bfa9aa8e099 > Author: Yunhong Jiang <yunhong.jiang@xxxxxxxxx> > Date: Mon Jun 13 14:20:01 2016 -0700 > > KVM: x86: support using the vmx preemption timer for tsc deadline timer > > The VMX preemption timer can be used to virtualize the TSC deadline timer. > The VMX preemption timer is armed when the vCPU is running, and a VMExit > will happen if the virtual TSC deadline timer expires. > > When the vCPU thread is blocked because of HLT, KVM will switch to use > an hrtimer, and then go back to the VMX preemption timer when the vCPU > thread is unblocked. > > This solution avoids the complex OS's hrtimer system, and the host > timer interrupt handling cost, replacing them with a little math > (for guest->host TSC and host TSC->preemption timer conversion) > and a cheaper VMexit. This benefits latency for isolated pCPUs. > > [A word about performance... Yunhong reported a 30% reduction in average > latency from cyclictest. I made a similar test with tscdeadline_latency > from kvm-unit-tests, and measured > > - ~20 clock cycles loss (out of ~3200, so less than 1% but still > statistically significant) in the worst case where the test halts > just after programming the TSC deadline timer > > - ~800 clock cycles gain (25% reduction in latency) in the best case > where the test busy waits. > > I removed the VMX bits from Yunhong's patch, to concentrate them in the > next patch - Paolo] > > Signed-off-by: Yunhong Jiang <yunhong.jiang@xxxxxxxxx> > Signed-off-by: Paolo Bonzini <pbonzini@xxxxxxxxxx>
