On Mon, Aug 5, 2019 at 5:08 PM Christian Borntraeger <borntraeger@xxxxxxxxxx> wrote: > > > > On 02.08.19 09:47, Anup Patel wrote: > > For KVM RISC-V, we use KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls to access > > VCPU config and registers from user-space. > > > > We have three types of VCPU registers: > > 1. CONFIG - these are VCPU config and capabilities > > 2. CORE - these are VCPU general purpose registers > > 3. CSR - these are VCPU control and status registers > > > > The CONFIG registers available to user-space are ISA and TIMEBASE. Out > > of these, TIMEBASE is a read-only register which inform user-space about > > VCPU timer base frequency. The ISA register is a read and write register > > where user-space can only write the desired VCPU ISA capabilities before > > running the VCPU. > > > > The CORE registers available to user-space are PC, RA, SP, GP, TP, A0-A7, > > T0-T6, S0-S11 and MODE. Most of these are RISC-V general registers except > > PC and MODE. The PC register represents program counter whereas the MODE > > register represent VCPU privilege mode (i.e. S/U-mode). > > > > The CSRs available to user-space are SSTATUS, SIE, STVEC, SSCRATCH, SEPC, > > SCAUSE, STVAL, SIP, and SATP. All of these are read/write registers. > > > > In future, more VCPU register types will be added (such as FP) for the > > KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls. > > While have ONE_REG will certainly work, have you considered the sync_reg scheme > (registers as part of kvm_run structure) > This will speed up the exit to QEMU as you do not have to do multiple ioctls > (each imposing a systemcall overhead) for one exit. > > Ideally you should not exit too often into qemu, but for those cases sync_regs > is faster than ONE_REG. > We will certainly explore sync_regs interface. Reducing exits to user-space will definitely help. This is the first series for KVM RISC-V so here we want to establish a stable and extensible UAPI header using which we will add support to QEMU KVM. For time being, we are using KVMTOOL for debug and development. Thanks, Anup
