> On Jun 26, 2019, at 3:32 PM, Krish Sadhukhan <krish.sadhukhan@xxxxxxxxxx> wrote:
>
>
> On 6/25/19 5:06 AM, Nadav Amit wrote:
>> Cc: Marc Orr <marcorr@xxxxxxxxxx>
>> Signed-off-by: Nadav Amit <nadav.amit@xxxxxxxxx>
>> ---
>> lib/x86/apic.h | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/lib/x86/apic.h b/lib/x86/apic.h
>> index 537fdfb..b5bf208 100644
>> --- a/lib/x86/apic.h
>> +++ b/lib/x86/apic.h
>> @@ -75,6 +75,7 @@ static inline bool x2apic_reg_reserved(u32 reg)
>> switch (reg) {
>> case 0x000 ... 0x010:
>> case 0x040 ... 0x070:
>> + case 0x090:
>> case 0x0c0:
>> case 0x0e0:
>> case 0x290 ... 0x2e0:
>
>
> 0x02f0 which is also reserved, is missing from the above list.
I tried adding it, and I get on bare-metal:
FAIL: x2apic - reading 0x2f0: x2APIC op triggered GP.
And actually, the SDM table 10-6 “Local APIC Register Address Map Supported
by x2APIC” also shows this register (LVT CMCI) as "Read/write”. So I don’t
know why you say it is reserved.
