On 6/17/2019 11:39 AM, Xiaoyao Li wrote:
On 6/16/2019 11:35 PM, Tao Xu wrote:UMWAIT and TPAUSE instructions use IA32_UMWAIT_CONTROL at MSR index E1H to determines the maximum time in TSC-quanta that the processor can reside in either C0.1 or C0.2. This patch is to Add support for save/load IA32_UMWAIT_CONTROL MSR in guest. Co-developed-by: Jingqi Liu <jingqi.liu@xxxxxxxxx> Signed-off-by: Jingqi Liu <jingqi.liu@xxxxxxxxx> Signed-off-by: Tao Xu <tao3.xu@xxxxxxxxx> --- no changes in v3: --- target/i386/cpu.h | 2 ++ target/i386/kvm.c | 13 +++++++++++++ target/i386/machine.c | 20 ++++++++++++++++++++ 3 files changed, 35 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 2f7c57a3c2..eb98b2e54a 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -450,6 +450,7 @@ typedef enum X86Seg { #define MSR_IA32_BNDCFGS 0x00000d90 #define MSR_IA32_XSS 0x00000da0 +#define MSR_IA32_UMWAIT_CONTROL 0xe1 #define XSTATE_FP_BIT 0 #define XSTATE_SSE_BIT 1 @@ -1348,6 +1349,7 @@ typedef struct CPUX86State { uint16_t fpregs_format_vmstate; uint64_t xss; + uint64_t umwait; TPRAccess tpr_access_type; } CPUX86State; diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 3efdb90f11..506c7cd038 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -91,6 +91,7 @@ static bool has_msr_hv_stimer; static bool has_msr_hv_frequencies; static bool has_msr_hv_reenlightenment; static bool has_msr_xss; +static bool has_msr_umwait; static bool has_msr_spec_ctrl; static bool has_msr_virt_ssbd; static bool has_msr_smi_count; @@ -1486,6 +1487,9 @@ static int kvm_get_supported_msrs(KVMState *s) case MSR_IA32_XSS: has_msr_xss = true; break; + case MSR_IA32_UMWAIT_CONTROL: + has_msr_umwait = true; + break;Need to add MSR_IA32_UMWAIT_CONTROL into msrs_to_save[] in your kvm patches, otherwise qemu never goes into this case.
OK, thank you for your suggestion. I will add it in the next version.
