A new MSR_IA32_CORE_CAP (0xcf) is defined. Each bit in the MSR enumerates a model specific feature. Currently bit 5 enumerates split lock detection. When bit 5 is 1, split lock detection is supported. When the bit is 0, split lock detection is not supported. Please check the latest Intel 64 and IA-32 Architectures Software Developer's Manual for more detailed information on the MSR and the split lock detection bit. Signed-off-by: Fenghua Yu <fenghua.yu@xxxxxxxxx> --- arch/x86/include/asm/msr-index.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 979ef971cc78..8b2a7899f784 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -61,6 +61,10 @@ #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 #define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) +#define MSR_IA32_CORE_CAP 0x000000cf +#define MSR_IA32_CORE_CAP_SPLIT_LOCK_DETECT_BIT 5 +#define MSR_IA32_CORE_CAP_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAP_SPLIT_LOCK_DETECT_BIT) + #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 #define NHM_C3_AUTO_DEMOTE (1UL << 25) #define NHM_C1_AUTO_DEMOTE (1UL << 26) -- 2.19.1
