Hi All, It's a great pleasure to inform everyone that we have RISC-V hypervisor extension available for QEMU and along with it we also have Xvisor (a baremetal type-1 hypervisor) working on QEMU with RISC-V hypervisor extension. Currently, we are able to boot two Linux RV64 Guests on Xvisor RV64. This will be very useful to RISC-V CPU designers in validating their implementation of RISC-V hypervisor extensions. The QEMU RISC-V hypervisor emulation is done by Alistair and is available in riscv-hyp-work.next branch at: https://github.com/alistair23/qemu.git. At the moment, QEMU RISC-V hypervisor emulation patches are on QEMU mailing list for review. (Refer, https://lists.gnu.org/archive/html/qemu-devel/2019-05/msg06064.html) The Xvisor RISC-V port is done by myself (Anup) and Atish. It can be found in master branch of Xvisor staging repo at: https://github.com/avpatel/xvisor-next.git. For more details on Xvisor, refer http://xhypervisor.org/ http://xhypervisor.org/index.php?page=news/20150427 The SBI runtime needs to support RISC-V hypervisor extensions. Particularly, we need to handle trap redirection, misaligned load/store emulation, and missing CSR emulation differently for HS-mode and VS-mode. We have extended OpenSBI to support RISC-V hypervisor extension and it is available in hyp_ext_changes_v1 branch at: https://github.com/riscv/opensbi.git We have made great progress in KVM RISC-V (type-2 hypervisor) as well. Currently, we are debugging KVM RISC-V and KVMTOOL RISC-V port on QEMU. You can expect RFC patches soon in June/July 2019. The KVM RISC-V can be found in riscv_kvm_v1 branch at: https://github.com/avpatel/linux.git The KVMTOOL RISC-V port can be found in riscv_v1 branch at: https://github.com/avpatel/kvmtool.git There is an early work on Xen RISC-V port which is avaliable in alistair/riscv-port branch at: https://github.com/alistair23/xen.git We will be showing a demo of QEMU+OpenSBI+Xvisor+Linux at up-coming RISC-V Zurich Workshop. (Refer, https://tmt.knect365.com/risc-v-workshop-zurich/) Stay tuned for more exciting updates on RISC-V hypervisors. Regards, Anup
