On 02/05/19 19:41, nadav.amit@xxxxxxxxx wrote: > From: Nadav Amit <nadav.amit@xxxxxxxxx> > > According to the SDM: "When a performance monitoring counters interrupt > is generated, the mask bit for its associated LVT entry is set." > > Unmask LVTPC on each interrupt by reprogramming it. As the old value is > known, no need for read-modify-write is needed. > > Signed-off-by: Nadav Amit <nadav.amit@xxxxxxxxx> > --- > x86/pmu.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/x86/pmu.c b/x86/pmu.c > index f7b3010..6658fe9 100644 > --- a/x86/pmu.c > +++ b/x86/pmu.c > @@ -184,6 +184,7 @@ static void start_event(pmu_counter_t *evt) > wrmsr(MSR_CORE_PERF_FIXED_CTR_CTRL, ctrl); > } > global_enable(evt); > + apic_write(APIC_LVTPC, PC_VECTOR); > } > > static void stop_event(pmu_counter_t *evt) > Queued, thanks. Paolo
