On 14/05/19 08:06, Wanpeng Li wrote:
> From: Wanpeng Li <wanpengli@xxxxxxxxxxx>
>
> The CPUID.01H:ECX[bit 3] ought to mirror the value of the MSR
> IA32_MISC_ENABLE MWAIT bit and as userspace has control of them
> both, it is userspace's job to configure both bits to match on
> the initial setup.
Queued, thanks.
Paolo
> Cc: Eduardo Habkost <ehabkost@xxxxxxxxxx>
> Cc: Paolo Bonzini <pbonzini@xxxxxxxxxx>
> Cc: Radim Krčmář <rkrcmar@xxxxxxxxxx>
> Signed-off-by: Wanpeng Li <wanpengli@xxxxxxxxxxx>
> ---
> target/i386/cpu.c | 3 +++
> target/i386/cpu.h | 1 +
> 2 files changed, 4 insertions(+)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 722c551..40b6108 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -4729,6 +4729,9 @@ static void x86_cpu_reset(CPUState *s)
>
> env->pat = 0x0007040600070406ULL;
> env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
> + if (enable_cpu_pm) {
> + env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
> + }
>
> memset(env->dr, 0, sizeof(env->dr));
> env->dr[6] = DR6_FIXED_1;
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 0128910..b94c329 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -387,6 +387,7 @@ typedef enum X86Seg {
> #define MSR_IA32_MISC_ENABLE 0x1a0
> /* Indicates good rep/movs microcode on some processors: */
> #define MSR_IA32_MISC_ENABLE_DEFAULT 1
> +#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
>
> #define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
> #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
>
