[kvm-unit-tests PATCH] Remove non-ASCII characters from vmx_tests.c

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Some of the comments in vmx_test.c were copy/pasted from the SDM, and
include non-ASCII characters, which may not render properly in some
software engineering environments (e.g., vi). Thus, let's replace these
with their dumber, but superior, ASCII equivalents.

Signed-off-by: Marc Orr <marcorr@xxxxxxxxxx>
Reviewed-by: Peter Shier <pshier@xxxxxxxxxx>
Reviewed-by: Jim Mattson <jmattson@xxxxxxxxxx>
---
 x86/vmx_tests.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/x86/vmx_tests.c b/x86/vmx_tests.c
index 2acc219e1b98..47af84653e5c 100644
--- a/x86/vmx_tests.c
+++ b/x86/vmx_tests.c
@@ -3872,13 +3872,13 @@ static void test_pi_desc_addr(u64 addr, bool ctrl)
 }
 
 /*
- * If the “process posted interrupts†VM-execution control is 1, the
+ * If the "process posted interrupts" VM-execution control is 1, the
  * following must be true:
  *
- *	- The “virtual-interrupt delivery†VM-execution control is 1.
- *	- The “acknowledge interrupt on exit†VM-exit control is 1.
+ *	- The "virtual-interrupt delivery" VM-execution control is 1.
+ *	- The "acknowledge interrupt on exit" VM-exit control is 1.
  *	- The posted-interrupt notification vector has a value in the
- *	- range 0–255 (bits 15:8 are all 0).
+ *	- range 0-255 (bits 15:8 are all 0).
  *	- Bits 5:0 of the posted-interrupt descriptor address are all 0.
  *	- The posted-interrupt descriptor address does not set any bits
  *	  beyond the processor's physical-address width.
@@ -4002,7 +4002,7 @@ static void test_apic_ctls(void)
 }
 
 /*
- * If the “enable VPID†VM-execution control is 1, the value of the
+ * If the "enable VPID" VM-execution control is 1, the value of the
  * of the VPID VM-execution control field must not be 0000H.
  * [Intel SDM]
  */
@@ -4924,14 +4924,14 @@ static void test_vm_execution_ctls(void)
   * the VM-entry MSR-load count field is non-zero:
   *
   *    - The lower 4 bits of the VM-entry MSR-load address must be 0.
-  *      The address should not set any bits beyond the processor’s
+  *      The address should not set any bits beyond the processor's
   *      physical-address width.
   *
   *    - The address of the last byte in the VM-entry MSR-load area
-  *      should not set any bits beyond the processor’s physical-address
+  *      should not set any bits beyond the processor's physical-address
   *      width. The address of this last byte is VM-entry MSR-load address
   *      + (MSR count * 16) - 1. (The arithmetic used for the computation
-  *      uses more bits than the processor’s physical-address width.)
+  *      uses more bits than the processor's physical-address width.)
   *
   *
   *  [Intel SDM]
@@ -5148,7 +5148,7 @@ static void test_ctl_reg(const char *cr_name, u64 cr, u64 fixed0, u64 fixed1)
  *    operation.
  * 3. On processors that support Intel 64 architecture, the CR3 field must
  *    be such that bits 63:52 and bits in the range 51:32 beyond the
- *    processor’s physical-address width must be 0.
+ *    processor's physical-address width must be 0.
  *
  *  [Intel SDM]
  */
-- 
2.21.0.392.gf8f6787159e-goog





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