> From: Hansen, Dave > On 3/1/19 6:44 PM, Fenghua Yu wrote: > > diff --git a/arch/x86/include/asm/cpufeatures.h > b/arch/x86/include/asm/cpufeatures.h > > index 6d6122524711..350eeccd0ce9 100644 > > --- a/arch/x86/include/asm/cpufeatures.h > > +++ b/arch/x86/include/asm/cpufeatures.h > > @@ -349,6 +349,7 @@ > > #define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single > Thread Indirect Branch Predictors */ > > #define X86_FEATURE_FLUSH_L1D (18*32+28) /* Flush L1D > cache */ > > #define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* > IA32_ARCH_CAPABILITIES MSR (Intel) */ > > +#define X86_FEATURE_CORE_CAPABILITY (18*32+30) /* > IA32_CORE_CAPABILITY MSR */ > > #define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* "" Speculative > Store Bypass Disable */ > > What does this feature end up looking like in /proc/cpuinfo? The flag string is "core_capability" in /proc/cpuinfo. Thanks. -Fenghua
