On Friday, February 15, 2019 12:32 AM, Andi Kleen wrote:
>
> > +static void intel_pmu_get_global_status(struct kvm_pmu *pmu,
> > + struct msr_data *msr_info)
> > +{
> > + u64 guest_debugctl, freeze_lbr_bits =
> DEBUGCTLMSR_FREEZE_LBRS_ON_PMI |
> > + DEBUGCTLMSR_LBR;
> > +
> > + if (!pmu->global_status) {
> > + msr_info->data = 0;
> > + return;
> > + }
> > +
> > + msr_info->data = pmu->global_status;
> > + if (pmu->version >= 4) {
> > + guest_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
> > + if ((guest_debugctl & freeze_lbr_bits) == freeze_lbr_bits)
>
> It should only check for the freeze bit, the freeze bit can be set even when
> LBRs are disabled.
>
> Also you seem to set the bit unconditionally?
> That doesn't seem right. It should only be set after an overflow.
>
> So the PMI injection needs to set it.
OK. The freeze bits need to be cleared by IA32_PERF_GLOBAL_STATUS_RESET, which seems not supported by the perf code yet (thus guest won't clear them). Would handle_irq_v4 also need to be changed to support that?
Best,
Wei
