On 2/5/19 12:52 PM, Vitaly Kuznetsov wrote:
Zdenek Kaspar <zkaspar82@xxxxxxxxx> writes:
Hi,
old Core2 CPU: everything works well,
but I see once in dmesg (5.0-rc4):
unchecked MSR access error: RDMSR from 0x48b at rIP: 0xffffffffa0267570
(nested_vmx_setup_ctls_msrs+0xb0/0x210 [kvm_intel])
Oh,
0x48b is (MSR_IA32_VMX_PROCBASED_CTLS2) and SDM says we should only read
it "If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_CTLS[63])". I'm
guessing that you're not using nested but now it is enabled by default.
so the following (completely untested) patch should work for you:
diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
index 653830d0f3da..4bd0902bfd8c 100644
--- a/arch/x86/kvm/vmx/nested.c
+++ b/arch/x86/kvm/vmx/nested.c
@@ -5557,9 +5557,11 @@ void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs *msrs, u32 ept_caps,
* secondary cpu-based controls. Do not include those that
* depend on CPUID bits, they are added later by vmx_cpuid_update.
*/
- rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
- msrs->secondary_ctls_low,
- msrs->secondary_ctls_high);
+ if (msrs->procbased_ctls_high & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS)
+ rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
+ msrs->secondary_ctls_low,
+ msrs->secondary_ctls_high);
+
msrs->secondary_ctls_low = 0;
Please let me now if this helps.
Yes, patch is good.
5.0-rc5 boots fine with:
Intel(R) Core(TM)2 CPU 6600 @ 2.40GHz (family: 0x6, model:
0xf, stepping: 0x6)
Thanks, Z.
