According to section "Checks on VMX Controls" in Intel SDM vol 3C, the
following check is performed on vmentry of L2 guests:
On processors that support Intel 64 architecture, the IA32_SYSENTER_ESP
field and the IA32_SYSENTER_EIP field must each contain a canonical
address.
Signed-off-by: Krish Sadhukhan <krish.sadhukhan@xxxxxxxxxx>
Reviewed-by: Mihai Carabas <mihai.carabas@xxxxxxxxxx>
---
x86/vmx_tests.c | 39 +++++++++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/x86/vmx_tests.c b/x86/vmx_tests.c
index 9a3cdee..2e45e02 100644
--- a/x86/vmx_tests.c
+++ b/x86/vmx_tests.c
@@ -4909,6 +4909,44 @@ static void test_vm_exit_ctls(void)
test_exit_msr_store();
}
+/*
+ * On processors that support Intel 64 architecture, the IA32_SYSENTER_ESP
+ * field and the IA32_SYSENTER_EIP field must each contain a canonical
+ * address.
+ *
+ * [Intel SDM]
+ */
+static void test_host_ctl_regs(void)
+{
+ if (!is_canonical(vmcs_read(HOST_SYSENTER_ESP))) {
+ report_prefix_pushf("HOST_SYSENTER_ESP non-canonical");
+ test_vmx_controls(false, false);
+ report_prefix_pop();
+ } else {
+ report_prefix_pushf("HOST_SYSENTER_ESP canonical");
+ test_vmx_controls(true, false);
+ report_prefix_pop();
+ }
+
+ if (!is_canonical(vmcs_read(HOST_SYSENTER_EIP))) {
+ report_prefix_pushf("HOST_SYSENTER_EIP non-canonical");
+ test_vmx_controls(false, false);
+ report_prefix_pop();
+ } else {
+ report_prefix_pushf("HOST_SYSENTER_EIP canonical");
+ test_vmx_controls(true, false);
+ report_prefix_pop();
+ }
+}
+
+/*
+ * Tests for host control registers and MSRs
+ */
+static void test_vm_host_ctl_regs_msrs(void)
+{
+ test_host_ctl_regs();
+}
+
/*
* Check that the virtual CPU checks all of the VMX controls as
* documented in the Intel SDM.
@@ -4925,6 +4963,7 @@ static void vmx_controls_test(void)
test_vm_execution_ctls();
test_vm_exit_ctls();
test_vm_entry_ctls();
+ test_vm_host_ctl_regs_msrs();
}
static bool valid_vmcs_for_vmentry(void)
--
2.17.2
