On Fri, Dec 21, 2018 at 02:28:41PM +1100, Suraj Jitindar Singh wrote: > The shadow page table contains ptes for translations from nested guest > address to host address. Currently when creating these ptes we take the > rc bits from the pte for the L1 guest address to host address > translation. This is incorrect as we must also factor in the rc bits > from the pte for the nested guest address to L1 guest address > translation (as contained in the L1 guest partition table for the nested > guest). > > By not calculating these bits correctly L1 may not have been correctly > notified when it needed to update its rc bits in the partition table it > maintains for its nested guest. > > Modify the code so that the rc bits in the resultant pte for the L2->L0 > translation are the 'and' of the rc bits in the L2->L1 pte and the L1->L0 > pte, also accounting for whether this was a write access when setting > the dirty bit. > > Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@xxxxxxxxx> Reviewed-by: David Gibson <david@xxxxxxxxxxxxxxxxxxxxx> > --- > arch/powerpc/kvm/book3s_hv_nested.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/powerpc/kvm/book3s_hv_nested.c b/arch/powerpc/kvm/book3s_hv_nested.c > index 9dfb927ea14f..4a52f82649e5 100644 > --- a/arch/powerpc/kvm/book3s_hv_nested.c > +++ b/arch/powerpc/kvm/book3s_hv_nested.c > @@ -1235,6 +1235,9 @@ static long int __kvmhv_nested_page_fault(struct kvm_vcpu *vcpu, > perm |= gpte.may_read ? 0UL : _PAGE_READ; > perm |= gpte.may_write ? 0UL : _PAGE_WRITE; > perm |= gpte.may_execute ? 0UL : _PAGE_EXEC; > + /* Only set accessed/dirty (rc) bits if set in host and l1 guest ptes */ > + perm |= (gpte.rc & _PAGE_ACCESSED) ? 0UL : _PAGE_ACCESSED; > + perm |= ((gpte.rc & _PAGE_DIRTY) && writing) ? 0UL : _PAGE_DIRTY; > pte = __pte(pte_val(pte) & ~perm); > > /* What size pte can we insert? */ -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson
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