Re: [PATCH 00/10] x86: PTE D Bit based dirty logging

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On Sat, 20 Oct 2018 at 11:18, Junaid Shahid <junaids@xxxxxxxxxx> wrote:
>
> This patch series implements a new dirty logging mode utilizing the Dirty
> bits in the SPTEs, when available, instead of relying on write protection.
> On hosts that do not support PML, this can result in significant
> improvement in VM performance for some workloads during the brownout phase
> of a live migration when compared to write protection based dirty logging,
> because of the elimination of all the VM exits on memory writes.
>
> However, this new mode does incur additional time in the get_dirty_log
> IOCTL because of having to scan all the SPTEs for dirtiness, which can
> in some cases, result in slightly elongating the blackout time. Two
> strategies can be used to mitigate that. The first, included in this
> series, is to have the ability to dynamically switch between D Bit based
> and write protection based dirty logging modes. Then the mode could be
> switched to write protection just before entering blackout, thus incurring
> less time in the get_dirty_log IOCTL during blackout, while keeping the
> reduced overhead of the D Bit based mode during brownout. Secondly, the
> scan in the get_dirty_log IOCTL can be parallelized, which results in that
> IOCTL becoming faster for all modes. That patch series will be sent out
> separately a little later.

Interesting, I also implement a version of PTE D Bit based dirty
logging 4 years ago w/o sending to upstream. The PTE D Bit based mode
will switch to write protection mode each time before
KVM_GET_DIRTY_LOG ioctl or just once before the xx_start?

Regards,
Wanpeng Li



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