On Tue, Aug 28, 2018 at 12:21:40PM +0200, Borislav Petkov wrote: > On Mon, Aug 27, 2018 at 09:53:24PM +0300, Jarkko Sakkinen wrote: > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > > index 7bb647f57d42..4af60a0fdb20 100644 > > --- a/arch/x86/include/asm/cpufeatures.h > > +++ b/arch/x86/include/asm/cpufeatures.h > > @@ -13,7 +13,7 @@ > > /* > > * Defines x86 CPU feature bits > > */ > > -#define NCAPINTS 19 /* N 32-bit words worth of info */ > > +#define NCAPINTS 20 /* N 32-bit words worth of info */ > > #define NBUGINTS 1 /* N 32-bit bug flags */ > > > > /* > > @@ -349,6 +349,12 @@ > > #define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */ > > #define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* "" Speculative Store Bypass Disable */ > > > > +/* Intel SGX CPU features, CPUID level 0x000000012:0 (EAX), word 19 */ > > +#define X86_FEATURE_SGX1 (19*32+ 0) /* SGX1 leaf functions */ > > +#define X86_FEATURE_SGX2 (19*32+ 1) /* SGX2 leaf functions */ > > +#define X86_FEATURE_SGX_ENCLV (19*32+ 5) /* SGX ENCLV instruction, leafs E[INC|DEC]VIRTCHILD, ESETCONTEXT */ > > +#define X86_FEATURE_SGX_ENCLS_C (19*32+ 6) /* SGX ENCLS leafs ERDINFO, ETRACK, ELDBC and ELDUC */ > > No need to add a whole new ->x86_capability member for 4 bits - just add > those bits to leaf 8 where the artificial virtualization flags are - > there's some room there. > > Thx. Roger. > > -- > Regards/Gruss, > Boris. > > SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nürnberg) > -- /Jarkko
