See Intel's instructions for determining the processor base frequency in volume 3 of the SDM: 18.7.3.1 For Intel Processors Based on Microarchitecture Code Name Sandy Bridge, Ivy Bridge, Haswell and Broadwell The scalable bus frequency is encoded in the bit field MSR_PLATFORM_INFO[15:8] and the nominal TSC frequency can be determined by multiplying this number by a bus speed of 100 MHz. If MSR_PLATFORM_INFO[15:8] reads as zero, the nominal TSC frequency is zero. On Mon, Aug 13, 2018 at 6:48 AM, Konrad Rzeszutek Wilk <konrad.wilk@xxxxxxxxxx> wrote: > On Fri, Aug 10, 2018 at 02:26:02PM -0700, Drew Schmitt wrote: >> Allow userspace to set turbo bits in MSR_PLATFORM_INFO. Previously, only >> the CPUID faulting bit was settable. But now any bit in >> MSR_PLATFORM_INFO would be settable. > > Can you include the rationale of why this is need please? > > >> >> Signed-off-by: Drew Schmitt <dasch@xxxxxxxxxx> >> --- >> arch/x86/kvm/x86.c | 1 - >> 1 file changed, 1 deletion(-) >> >> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c >> index 0046aa70205aa..0278cde1893ca 100644 >> --- a/arch/x86/kvm/x86.c >> +++ b/arch/x86/kvm/x86.c >> @@ -2503,7 +2503,6 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) >> break; >> case MSR_PLATFORM_INFO: >> if (!msr_info->host_initiated || >> - data & ~MSR_PLATFORM_INFO_CPUID_FAULT || >> (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) && >> cpuid_fault_enabled(vcpu))) >> return 1; >> -- >> 2.18.0.597.ga71716f1ad-goog >>
