On Fri, Aug 10, 2018 at 05:48:36PM +0100, Alan Cox wrote: > > The hardware isn't public yet, so can't talk about it :-(. Once this patch gets > > merged, will let the OSV engagement folks drive it for inclusions. We > > could mark this for stable, but i would rather wait until we know the > > timeline when they are expecting it to be in. It shouldn't break anything > > since we are just enforcing the spec. > > Until a new better spec appears... Well, here we are talking about PIN interrupts and VF's. IMO it would be weird to allow Virtual functions and physical interrupts other than MSIx. There are other things in the PCIe spec which could be enforced in SW or expect devices to implement them. What might be ok is probably doing the right thing in SW as done in this patch, additionaly maybe we can flag them and say "Your device is busted" message. > > I know there is always fun when it comes to the people involved in > such a screwup having to admit it in public but this should IMHO be > tied to a PCI identifier table so that we know what the afflicted > hardware is. Otherwise some day in the future SRIOV will grow new features > and we'll have no idea what particular devices we need to narrow the > workaround too and indeed not necessarily even know this device is the > only one, as we'll silently fix other stuff then have it break on us > later. > > Alan