On Fri, Jul 20, 2018 at 04:39:42PM +0100, Andre Przywara wrote: > Some tests for the ITARGETS registers. > Bits corresponding to non-existent CPUs must be RAZ/WI. > These registers must be byte-accessible, also check that accesses beyond > the implemented IRQ limit are actually read-as-zero/write-ignore. > > Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx> > --- > arm/gic.c | 43 +++++++++++++++++++++++++++++++++++++++++++ > lib/arm/asm/gic.h | 1 + > 2 files changed, 44 insertions(+) > Reviewed-by: Andrew Jones <drjones@xxxxxxxxxx>
