On Tue, Jul 24, 2018 at 01:08:49PM +0200,
Paolo Bonzini <pbonzini@xxxxxxxxxx> wrote:
> On 23/07/2018 23:16, Isaku Yamahata wrote:
> > Optimize latency of TSC deadline emulation by skipping various KVM related
> > checks when opssible. i.e. On VMExit for tsc deadline timer emulation,
> > handle it and VMEnter immidiately without checking various kvm stuff
> > when possible.
> > The result can be measured by cyclic test in guest and ftracing
> > local timer interrupt entry(irq_vectors:local_timer_exit).
> > On local machine, average latency can be reduced by tens of microseconds.
>
> The latency of the TSC deadline timer is already around 2-5
> microseconds, isn't it?
I meant the result of cyclic test. which includes
host kvm, guest kernel, cyclic test process in guest.
You mean the really kvm module execution path.
Probably With cyclic test, cache pollution would affect.
On the other hand, vmext.flat is very small.
> What is the result on kvm-unit-tests' vmexit.flat (the tscdeadline and
> tscdeadline_immed benchmarks are the interesting ones)?
Here is the result of average of 100 run on my environment.
In this case, I removed the 1st patch which was wrong
and also optimized MSR EOI path.
average of 100 run
enabled fastpath
tscdeadline 8325.76
tscdeadline_immed 6087.41
disabled fastpath
tscdeadline 9922.06
tscdeadline_immed 6388.83
thanks,
--
Isaku Yamahata <isaku.yamahata@xxxxxxxxx>
