On 06/27/2018 02:59 PM, Junaid Shahid wrote: > Changes since v2: > - CR3_PCID_INVD is replaced by X86_CR3_PCID_NOFLUSH > - kvm_mmu_calc_root_page_role() and friends are no longer public > - Simplified the race condition example in mmu_need_write_protect() > - Added smp_load_acquire()s in kvm_mmu_sync_roots() > - Ignored non-canonical addresses in vmx_flush_tlb_gva() > - A couple of minor cleanups > > Changes since v1: > - Renamed the flags returned by set_spte > - Split up a couple of changes into separate patches and refactored some > other patches > - .set_cr3() handlers never flush TLB rather than taking that as parameter > - Generalized lockless CR3 switching to work acroos different MMU modes > - Implemented lockless CR3/EPTP switching for nested VMX L1<->L2 switches > - Added an LRU cache containing multiple fast-switchable roots instead > of limiting it to only the immediately previous one. > > The performance of shadow paging is severely degraded in some workloads > when the guest kernel is using KPTI. This is primarily due to the vastly > increased number of CR3 switches that result from KPTI. > > This patch series implements various optimizations to reduce some of this > overhead. Compared to the baseline, this results in a reduction from > ~16m12s to ~4m44s for a 4-VCPU kernel compile benchmark and from ~25m5s to > ~14m50s for a 1-VCPU kernel compile benchmark. > Hi Paolo, I was just wondering if this series is good to go? Thanks, Junaid
