> -----Original Message----- > From: Alexander Shishkin [mailto:alexander.shishkin@xxxxxxxxxxxxxxx] > Sent: Thursday, July 5, 2018 7:54 PM > To: Kang, Luwei <luwei.kang@xxxxxxxxx> > Cc: kvm@xxxxxxxxxxxxxxx; x86@xxxxxxxxxx; Kang, Luwei <luwei.kang@xxxxxxxxx>; Thomas Gleixner <tglx@xxxxxxxxxxxxx>; Ingo > Molnar <mingo@xxxxxxxxxx>; H. Peter Anvin <hpa@xxxxxxxxx>; Peter Zijlstra (Intel) <peterz@xxxxxxxxxxxxx>; Alexander Shishkin > <alexander.shishkin@xxxxxxxxxxxxxxx>; Song Liu <songliubraving@xxxxxx>; Kate Stewart <kstewart@xxxxxxxxxxxxxxxxxxx>; Greg > Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> > Subject: Re: [PATCH v10 04/12] perf/x86/intel/pt: add new capability for Intel PT > > Luwei Kang <luwei.kang@xxxxxxxxx> writes: > > > CPUID(EAX=14H,ECX=0):EBX[bit 3] = 1 indicates support of output to > > Trace Transport subsystem. MSR IA32_RTIT_CTL.FabricEn[bit 6] is > > reserved if CPUID.(EAX=14H, ECX=0):ECX[bit 3] = 0. > > This paragraph should go. The next paragraph is a good opener for this patch. > > > This adds support for "output to Trace Transport subsystem" capability > > of Intel PT. It means that PT can output its trace to an MMIO address > > range rather than system memory buffer. > > > > This also used by KVM for IA32_RTIT_CTL MSR read/write emulation. > > KVM guest write IA32_RTIT_CTL will be trapped to root mode and a #GP > > would be injected to guest if set IA32_RTIT_CTL.FabricEn with > > CPUID.(EAX=14H, ECX=0):ECX[bit 3] = 0. > > This paragraph also doesn't belong here as this patch doesn't have anything to do with KVM. > Thanks for your review, will remove then and just keep: This adds support for "output to Trace Transport subsystem" capability of Intel PT. It means that PT can output its trace to an MMIO address range rather than system memory buffer. Have any comments on this patch set? Especially the changes in native? Thanks, Luwei Kang
