On 06/13/2018 11:53 AM, Sean Christopherson wrote:
>>> /*
>>> * Mappings not reachable via the current cr3 will be synced when
>>> - * switching to that cr3, so nothing needs to be done here for them.
>>> + * switching to that cr3, so nothing needs to be synced here for them.
>>
>> Hmm, IMO this comment and the similar comment for the single context
>> case should either be updated to explicitly call out that we also need
>> to flush the TLB if the PCID matches that of the fast CR3 cache, or
>> simply removed altogether.
>
> Just saw that you do update the comment in PATCH 15/17, maybe part or
> all of the comment update should be moved to this patch?
Ok. I'll update the comments in this patch.
>>> - if (pcid_enabled)
>>> + if (pcid_enabled) {
>>> + skip_tlb_flush = cr3 & CR3_PCID_INVD;
>>> cr3 &= ~CR3_PCID_INVD;
>>
>> While you're here, could you remove KVM's CR3_PCID_INVD define and
>> use the kernel's X86_CR3_PCID_NOFLUSH define? Duplication aside,
>> CR3_PCID_INVD is a terrible name since it inverts the logic.
Sure. I'll remove that.
Thanks,
Junaid
