RE: [PATCH v14 2/6] i386: Enable TOPOEXT feature on AMD EPYC CPU

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> -----Original Message-----
> From: kvm-owner@xxxxxxxxxxxxxxx [mailto:kvm-owner@xxxxxxxxxxxxxxx]
> On Behalf Of Moger, Babu
> Sent: Thursday, June 14, 2018 3:41 PM
> To: Eduardo Habkost <ehabkost@xxxxxxxxxx>
> Cc: mst@xxxxxxxxxx; marcel.apfelbaum@xxxxxxxxx; pbonzini@xxxxxxxxxx;
> rth@xxxxxxxxxxx; mtosatti@xxxxxxxxxx; qemu-devel@xxxxxxxxxx;
> kvm@xxxxxxxxxxxxxxx; kash@xxxxxxxxxxxxxx; geoff@xxxxxxxxxxxxxxx
> Subject: RE: [PATCH v14 2/6] i386: Enable TOPOEXT feature on AMD EPYC
> CPU
> 
> 
> 
> > -----Original Message-----
> > From: Eduardo Habkost [mailto:ehabkost@xxxxxxxxxx]
> > Sent: Thursday, June 14, 2018 1:40 PM
> > To: Moger, Babu <Babu.Moger@xxxxxxx>
> > Cc: mst@xxxxxxxxxx; marcel.apfelbaum@xxxxxxxxx;
> pbonzini@xxxxxxxxxx;
> > rth@xxxxxxxxxxx; mtosatti@xxxxxxxxxx; qemu-devel@xxxxxxxxxx;
> > kvm@xxxxxxxxxxxxxxx; kash@xxxxxxxxxxxxxx; geoff@xxxxxxxxxxxxxxx
> > Subject: Re: [PATCH v14 2/6] i386: Enable TOPOEXT feature on AMD EPYC
> > CPU
> >
> > On Wed, Jun 13, 2018 at 09:18:23PM -0400, Babu Moger wrote:
> > > Enable TOPOEXT feature on EPYC CPU. This is required to support
> > > hyperthreading on VM guests. Also extend xlevel to 0x8000001E.
> > >
> > > Signed-off-by: Babu Moger <babu.moger@xxxxxxx>
> > > ---
> > >  target/i386/cpu.c | 11 +++++++++--
> > >  1 file changed, 9 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> > > index 86fb1a4..2eb26da 100644
> > > --- a/target/i386/cpu.c
> > > +++ b/target/i386/cpu.c
> > > @@ -2554,7 +2554,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
> > >          .features[FEAT_8000_0001_ECX] =
> > >              CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
> > >              CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
> > CPUID_EXT3_ABM |
> > > -            CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM |
> CPUID_EXT3_LAHF_LM,
> > > +            CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM |
> CPUID_EXT3_LAHF_LM
> > |
> > > +            CPUID_EXT3_TOPOEXT,
> > >          .features[FEAT_7_0_EBX] =
> > >              CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
> > CPUID_7_0_EBX_AVX2 |
> > >              CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 |
> > CPUID_7_0_EBX_RDSEED |
> > > @@ -2599,7 +2600,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
> > >          .features[FEAT_8000_0001_ECX] =
> > >              CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
> > >              CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
> > CPUID_EXT3_ABM |
> > > -            CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM |
> CPUID_EXT3_LAHF_LM,
> > > +            CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM |
> CPUID_EXT3_LAHF_LM
> > |
> > > +            CPUID_EXT3_TOPOEXT,
> > >          .features[FEAT_8000_0008_EBX] =
> > >              CPUID_8000_0008_EBX_IBPB,
> > >          .features[FEAT_7_0_EBX] =
> >
> > This part is OK, but it requires patch 3/6 to be included in the
> > same patch.
> 
> Ok. Sure.
> >
> > > @@ -4667,6 +4669,11 @@ static void x86_cpu_expand_features(X86CPU
> > *cpu, Error **errp)
> > >              x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel,
> 0x8000000A);
> > >          }
> > >
> > > +        /* TOPOEXT feature requires 0x8000001E */
> > > +        if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT)
> {
> > > +            x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel,
> 0x8000001E);
> > > +        }
> >
> > This part needs to be done more carefully to avoid breaking
> > compatibility.  "-machine pc-q35-2.12 -cpu Opteron_G5,+topoext"
> > currently results in xlevel=0x8000001A, and this must not change.

Not sure if this could be a problem.  "+topoext" sets the feature bits. But xlevel is still 0x8000001A which does not look right.
I need to verify this case.
 
> Ok.
> >
> > I suggest just changing setting .xlevel=0x8000001E on EPYC at
> > builtin_x86_defs[1], and worry about automatically increasing
> > xlevel later.
> Ok.
> >
> > (If you change EPYC.xlevel in builtin_x86_defs, don't forget to
> > set EPYC.xlevel=0x8000000A on PC_COMPAT_2_12)
> Sure.
> >
> > --
> > Eduardo




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