Hi there, I have a question regarding to how the guest can update the next timer event without a VM-exit due to the MSR write. In the Chapter 29.5 of Intel Software Developer Manual (SDM), "Virtualizing MSR-Based APIC Access", for WRMSR: If special processing does not apply, the instruction operates normally. If the local APIC is in x2APIC mode and ECX indicates a writable APIC register, the value in EDX:EAX is written to that register. For example, the local APIC is in the x2APIC mode and the timer is in the one-shot mode in both the host and guest. The guest has its own dedicated core. After the local APIC timer fires and the local timer interrupt is handled as a virtual timer interrupt, the guest would like to set up the next timer event by updating LAPIC initial count register (TMICT), which has the register address at 0x838. Currently, this induces a VM exit and KVM handles the MSR write for the guest. According to the SDM, this address is writable and is not one of the special cases (TPR MSR, EOI MSR and Self IPI MSR). The next timer event should be written to TMICT. Then, why would such a guest timer update require the KVM's help? I feel I am missing something here. It would be great if you can point me to the right direction and other documentation related to the guest timer updates. Currently, I am also trying to see the effects if we disable the VMX intercepts on the MSR write to TMICT. Thanks. Best, Kevin
