This series enables the TOPOEXT feature for AMD CPUs. This is required to support hyperthreading on kvm guests. This addresses the issues reported in these bugs: https://bugzilla.redhat.com/show_bug.cgi?id=1481253 https://bugs.launchpad.net/qemu/+bug/1703506 v12: Patches are based off of Eduardo's git://github.com/ehabkost/qemu.git x86-next. Some of the patches are queued already. Submitting remaining series. Summary of changes. 1.Added more comments explaining CPUID_Fn8000001E bit definitions. 2.Split the patch into separate patch to check the topology. Moved the code to x86_cpu_realizefn. Display the error if topoext feature cannot be enabled. 3.Few more text corrections. v11: Patches are based off of Eduardo's git://github.com/ehabkost/qemu.git x86-next. Summary of changes. 1.Added more comments explaining different constants and variables. 2.Removed NUM_SHARING_CACHE macro and made the code simpler. 3.Changed the function name num_sharing_l3_cache to cores_in_core_complex. This function is actually finding the number of cores in a core complex. Purpose here is to re-use the code in couple more places. 4.Added new function nodes_in_socket to find number of nodes in the config. Purpose here is to re-use the code. 5.Used DIV_ROUND_UP wherever applicable. 6.Renamed few constants and functions to generic names. 7.Few more text corrections. v10: Based the patches on Eduardo's git://github.com/ehabkost/qemu.git x86-next Some of the earlier patches are already queued. So, submitting the rest of the series here. This series adds complete redesign of the cpu topology. Based on user given parameter, we try to build topology very close to the hardware. Maintains symmetry as much as possible. Added new function epyc_build_topology to build the topology based on user given nr_cores, nr_threads. Summary of changes. 1. Build the topology dinamically based on nr_cores and nr_threads 2. Added new epyc_build_topology to build the new topology. 3. Added new function num_sharing_l3_cache to calculate the L3 sharing 4. Added a check to verify the topology. Disabled the TOPOEXT if the topology cannot be built. v9: Based the patches on Eduardo's git://github.com/ehabkost/qemu.git x86-next tree. Following 3 patches from v8 are already queued. i386: Add cache information in X86CPUDefinition i386: Initialize cache information for EPYC family processors i386: Helpers to encode cache information consistently So, submitting the rest of the series here. Changes: 1. Included Eduardo's clean up patch 2. Added 2.13 machine types 3. Disabled topoext for 2.12 and below versions. 4. Added the assert to core_id as discussed. v8: Addressed feedback from Eduardo. Thanks Eduardo for being patient with me. Tested on AMD EPYC server and also did some basic testing on intel box. Summary of changes. 1. Reverted back l2 cache associativity. Kept it same as legacy. 2. Changed cache_info structure in X86CPUDefinition and CPUX86State to pointers. 3. Added legacy_cache property in PC_COMPAT_2_12 and initialized legacy_cache based on static cache_info availability. 4. Squashed patch 4 and 5 and applied it before patch 3. 5. Added legacy cache check for cpuid[2] and cpuid[4] for consistancy. 6. Simplified NUM_SHARING_CACHE definition for readability, 7. Removed assert for core_id as it appeared redundant. 8. Simplified encode_cache_cpuid8000001d little bit. 9. Few more minor changes v7: Rebased on top of latest tree after 2.12 release and done few basic tests. There are no changes except for few minor hunks. Hopefully this gets pulled into 2.13 release. Please review, let me know of any feedback. v6: 1.Fixed problem with patch#4(Add new property to control cache info). The parameter legacy_cache should be "on" by default on machine type "pc-q35-2.10". This was found by Alexandr Iarygin. 2.Fixed the l3 cache size for EPYC based machines(patch#3). Also, fixed the number of logical processors sharing the cache(patch#6). Only L3 cache is shared by multiple cores but not L1 or L2. This was a bug while decoding. This was found by Geoffrey McRae and he verified the fix. v5: In this series I tried to address the feedback from Eduardo Habkost. The discussion thread is here. https://patchwork.kernel.org/patch/10299745/ The previous thread is here. http://patchwork.ozlabs.org/cover/884885/ Reason for these changes. The cache properties for AMD family of processors have changed from previous releases. We don't want to display the new information on the old family of processors as this might cause compatibility issues. Changes: 1.Based the patches on top of Eduardo's(patch#1) patch. Changed few things. Moved the Cache definitions to cpu.h file. Changed the CPUID_4 names to generic names. 2.Added a new propery "legacy-cache" in cpu object(patch#2). This can be used to display the old property even if the host supports the new cache properties. 3.Added cache information in X86CPUDefinition and CPUX86State 4.Patch 6-7 changed quite a bit from previous version does to new approach. 5.Addressed few issues with CPUID_8000_001d and CPUID_8000_001E. v4: 1.Removed the checks under cpuid 0x8000001D leaf(patch #2). These check are not necessary. Found this during internal review. 2.Added CPUID_EXT3_TOPOEXT feature for all the 17 family(patch #4). This was found by Kash Pande during his testing. 3.Removed th hardcoded cpuid xlevel and dynamically extended if CPUID_EXT3_TOPOEXT is supported(Suggested by Brijesh Singh). v3: 1.Removed the patch #1. Radim mentioned that original typo problem is in linux kernel header. qemu is just copying those files. 2.In previous version, I used the cpuid 4 definitions for AMDs cpuid leaf 0x8000001D. CPUID 4 is very intel specific and we dont want to expose those details under AMD. I have renamed some of these definitions as generic. These changes are in patch#1. Radim, let me know if this is what you intended. 3.Added assert to for core_id(Suggested by Radim Krcmár). 4.Changed the if condition under "L3 cache info"(Suggested by Gary Hook). 5.Addressed few more text correction and code cleanup(Suggested by Thomas Lendacky). v2: Fixed few more minor issues per Gary Hook's comments. Thank you Gary. Removed the patch#1. We need to handle the instruction cache associativity seperately. It varies based on the cpu family. I will comeback to that later. Added two more typo corrections in patch#1 and patch#5. v1: Stanislav Lanci posted few patches earlier. https://patchwork.kernel.org/patch/10040903/ Rebased his patches with few changes. 1.Spit the patches into two, separating cpuid functions 0x8000001D and 0x8000001E (Patch 2 and 3). 2.Removed the generic non-intel check and made a separate patch with some changes(Patch 5). 3.Fixed L3_N_SETS_AMD(from 4096 to 8192) based on CPUID_Fn8000001D_ECX_x03. Added 2 more patches. Patch 1. Fixes cache associativity. Patch 4. Adds TOPOEXT feature on AMD EPYC CPU. Babu Moger (4): i386: Add support for CPUID_8000_001E for AMD i386: Verify if topoext feature can be supported i386: Enable TOPOEXT feature on AMD EPYC CPU i386: Remove generic SMT thread check include/hw/i386/pc.h | 4 ++ target/i386/cpu.c | 141 ++++++++++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 137 insertions(+), 8 deletions(-) -- 1.8.3.1
