On Mon, Jun 04, 2018 at 05:07:01PM -0300, Eduardo Habkost wrote: > On Fri, Jun 01, 2018 at 11:38:08AM -0400, Konrad Rzeszutek Wilk wrote: > > AMD future CPUs expose _two_ ways to utilize the Intel equivalant > > of the Speculative Store Bypass Disable. The first is via > > the virtualized VIRT_SPEC CTRL MSR (0xC001_011f) and the second > > is via the SPEC_CTRL MSR (0x48). The document titled: > > 124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf > > > > gives priority of SPEC CTRL MSR over the VIRT SPEC CTRL MSR. > > > > A copy of this document is available at > > https://bugzilla.kernel.org/show_bug.cgi?id=199889 > > > > Anyhow, this means that on future AMD CPUs there will be _two_ ways to > > deal with SSBD. > > Does anybody know if there are AMD CPUs where virt-ssbd won't > work and would require amd-ssbd to mitigate vulnerabilities? > > Also, do we have kernel arch/x86/kvm/cpuid.c patches, already? Not yet. They are being discussed right now. I figured I would send these patches out as a 'Hey, coming at you!', but failed to change the title to be 'RFC'. > I prefer to add new CPUID flag names only after the flag name is > already agreed upon on the kernel side. Of course. I will respin once that discussion has calmed down. > > > > > > Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@xxxxxxxxxx> > > --- > > target/i386/cpu.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > > index 52d334a..f91990c 100644 > > --- a/target/i386/cpu.c > > +++ b/target/i386/cpu.c > > @@ -490,7 +490,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { > > "ibpb", NULL, NULL, NULL, > > NULL, NULL, NULL, NULL, > > NULL, NULL, NULL, NULL, > > - NULL, "virt-ssbd", NULL, NULL, > > + "amd-ssbd", "virt-ssbd", NULL, NULL, > > NULL, NULL, NULL, NULL, > > }, > > .cpuid_eax = 0x80000008, > > -- > > 1.8.3.1 > > > > > > -- > Eduardo
