On Thu, May 17, 2018 at 11:35:45AM +0100, Marc Zyngier wrote: > Up to ARMv8.3, the combinaison of Stage-1 and Stage-2 attributes > results in the strongest attribute of the two stages. This means > that the hypervisor has to perform quite a lot of cache maintenance > just in case the guest has some non-cacheable mappings around. > > ARMv8.4 solves this problem by offering a different mode (FWB) where > Stage-2 has total control over the memory attribute (this is limited > to systems where both I/O and instruction caches are coherent with > the dcache). This is achieved by having a different set of memory > attributes in the page tables, and a new bit set in HCR_EL2. > > On such a system, we can then safely sidestep any form of dcache > management. > > Signed-off-by: Marc Zyngier <marc.zyngier@xxxxxxx> For the core arm64 bits: Acked-by: Catalin Marinas <catalin.marinas@xxxxxxx>
