Re: [v2, 1/5] powerpc: Add CPU feature bits for TM bug workarounds on POWER9 v2.2

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On Wed, 2018-03-21 at 10:31:59 UTC, Paul Mackerras wrote:
> This adds a CPU feature bit which is set for POWER9 "Nimbus" DD2.2
> processors which will be used to enable the hypervisor to assist
> hardware with the handling of checkpointed register values while the
> CPU is in suspend state, in order to work around hardware bugs.  The
> hardware assistance for these workarounds introduced a new hardware
> bug relating to the XER[SO] bit.  We add a separate feature bit for
> this bug in case future chips fix it while still requiring the
> hypervisor assistance with suspend state.
> 
> When the dt_cpu_ftrs subsystem is in use, the software assistance can
> be enabled using a "tm-suspend-hypervisor-assist" node in the device
> tree, and a "tm-suspend-xer-so-bug" node enables the workarounds for
> the XER[SO] bug.  In the absence of such nodes, a quirk enables both
> for POWER9 "Nimbus" DD2.2 processors.
> 
> Signed-off-by: Paul Mackerras <paulus@xxxxxxxxxx>

Series applied to powerpc next, thanks.

https://git.kernel.org/powerpc/c/b5af4f2793233cf37596e2c1f7b233

cheers



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