Jean-Philippe Brucker <jean-philippe.brucker@xxxxxxx> writes:
> Hi Punit,
>
> Thanks for the review
>
> On 09/03/18 16:53, Punit Agrawal wrote:
[...]
>>> +static void vfio_pci_msix_table_access(struct kvm_cpu *vcpu, u64 addr, u8 *data,
>>> + u32 len, u8 is_write, void *ptr)
>>> +{
>>> + struct kvm *kvm = vcpu->kvm;
>>> + struct vfio_pci_msi_entry *entry;
>>> + struct vfio_pci_device *pdev = ptr;
>>> + struct vfio_device *vdev = container_of(pdev, struct vfio_device, pci);
>>> +
>>> + u64 offset = addr - pdev->msix_table.guest_phys_addr;
>>> +
>>> + size_t vector = offset / PCI_MSIX_ENTRY_SIZE;
>>> + /* PCI spec says that software must use aligned 4 or 8 bytes accesses */
>>> + off_t field = offset % PCI_MSIX_ENTRY_SIZE;
>>
>> Does the 4/8 byte access assumption be checked? Or is this something
>> enforced before we get here.
>
> It's specific to MSI-X tables, so it would need to be checked here. The
> spec (6.8.2) says "undefined behaviour", so we're free to do whatever we
> want. I suppose we can return here
Makes sense. For unaligned accesses, it might be worth warning the user
to highlight the deviation from spec.
Thanks,
Punit
[...]
