On Fri, Feb 2, 2018 at 2:53 AM, Darren Kenny <darren.kenny@xxxxxxxxxx> wrote: > On Thu, Feb 01, 2018 at 10:59:44PM +0100, KarimAllah Ahmed wrote: >> >> Intel processors use MSR_IA32_ARCH_CAPABILITIES MSR to indicate RDCL_NO >> (bit 0) and IBRS_ALL (bit 1). This is a read-only MSR. By default the >> contents will come directly from the hardware, but user-space can still >> override it. >> >> [dwmw2: The bit in kvm_cpuid_7_0_edx_x86_features can be unconditional] >> >> Cc: Asit Mallick <asit.k.mallick@xxxxxxxxx> >> Cc: Dave Hansen <dave.hansen@xxxxxxxxx> >> Cc: Arjan Van De Ven <arjan.van.de.ven@xxxxxxxxx> >> Cc: Tim Chen <tim.c.chen@xxxxxxxxxxxxxxx> >> Cc: Linus Torvalds <torvalds@xxxxxxxxxxxxxxxxxxxx> >> Cc: Andrea Arcangeli <aarcange@xxxxxxxxxx> >> Cc: Andi Kleen <ak@xxxxxxxxxxxxxxx> >> Cc: Thomas Gleixner <tglx@xxxxxxxxxxxxx> >> Cc: Dan Williams <dan.j.williams@xxxxxxxxx> >> Cc: Jun Nakajima <jun.nakajima@xxxxxxxxx> >> Cc: Andy Lutomirski <luto@xxxxxxxxxx> >> Cc: Greg KH <gregkh@xxxxxxxxxxxxxxxxxxx> >> Cc: Paolo Bonzini <pbonzini@xxxxxxxxxx> >> Cc: Ashok Raj <ashok.raj@xxxxxxxxx> >> Reviewed-by: Paolo Bonzini <pbonzini@xxxxxxxxxx> >> Signed-off-by: KarimAllah Ahmed <karahmed@xxxxxxxxx> >> Signed-off-by: David Woodhouse <dwmw@xxxxxxxxxxxx> > > > Reviewed-by: Darren Kenny <darren.kenny@xxxxxxxxxx> Reviewed-by: Jim Mattson <jmattson@xxxxxxxxxx>
