On Tue, 2018-01-30 at 08:57 -0800, Jim Mattson wrote: > It's really hard to tell which patches are being proposed for which > repositories, but assuming that everything else is correct, I don't > think your condition is adequate. What if the physical CPU and the > virtual CPU both have CPUID.(EAX=7H,ECX=0):EDX[26], but only the > physical CPU has CPUID.(EAX=7H,ECX=0):EDX[27]? If the guest has write > access to MSR_IA32_SPEC_CTRL, it can set MSR_IA32_SPEC_CTRL[1] > (STIBP), even though setting that bit in the guest should raise #GP. Everything we're talking about here is for tip/x86/pti. Which I note has just updated to be 4.15-based, although I thought it was going to stay on 4.14 for now. So I've updated my tree at http://git.infradead.org/linux-retpoline.git/shortlog/refs/heads/ibpb accordingly. You can always write to the STIBP bit without a #GP even when it's not advertised/available. There's a possibility that we'll want to always trap and *prevent* that, instead of passing through — because doing so will also have an effect on the HT siblings. But as discussed, I wanted to get the basics working before exploring the complex IBRS/STIBP interactions. This much should be OK to start with.
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