Hi Paul, On Tue, Jan 23, 2018 at 07:30:33PM +1100, Paul Mackerras wrote: > On Thu, Jan 11, 2018 at 06:11:32PM +0800, wei.guo.simon@xxxxxxxxx wrote: > > From: Simon Guo <wei.guo.simon@xxxxxxxxx> > > > > Currently kernel doesn't use transaction memory. > > And there is an issue for privilege guest that: > > tbegin/tsuspend/tresume/tabort TM instructions can impact MSR TM bits > > without trap into PR host. So following code will lead to a false mfmsr > > result: > > tbegin <- MSR bits update to Transaction active. > > beq <- failover handler branch > > mfmsr <- still read MSR bits from magic page with > > transaction inactive. > > > > It is not an issue for non-privilege guest since its mfmsr is not patched > > with magic page and will always trap into PR host. > > > > This patch will always fail tbegin attempt for privilege guest, so that > > the above issue is prevented. It is benign since currently (guest) kernel > > doesn't initiate a transaction. > > > > Test case: > > https://github.com/justdoitqd/publicFiles/blob/master/test_tbegin_pr.c > > > > Signed-off-by: Simon Guo <wei.guo.simon@xxxxxxxxx> > > You need to handle the case where MSR_TM is not set in the guest MSR, > and give the guest a facility unavailable interrupt. Thanks for the catch. > > [snip] > > > --- a/arch/powerpc/kvm/book3s_pr.c > > +++ b/arch/powerpc/kvm/book3s_pr.c > > @@ -255,7 +255,7 @@ static inline void kvmppc_save_tm_sprs(struct kvm_vcpu *vcpu) > > tm_disable(); > > } > > > > -static inline void kvmppc_restore_tm_sprs(struct kvm_vcpu *vcpu) > > +inline void kvmppc_restore_tm_sprs(struct kvm_vcpu *vcpu) > > You should probably remove the 'inline' here too. OK. BR, - Simon
