Hi Paul, On Tue, Jan 23, 2018 at 06:29:27PM +1100, Paul Mackerras wrote: > On Thu, Jan 11, 2018 at 06:11:30PM +0800, wei.guo.simon@xxxxxxxxx wrote: > > ines: 219 > > > > From: Simon Guo <wei.guo.simon@xxxxxxxxx> > > > > The math registers will be saved into vcpu->arch.fp/vr and corresponding > > vcpu->arch.fp_tm/vr_tm area. > > > > We flush or giveup the math regs into vcpu->arch.fp/vr before saving > > transaction. After transaction is restored, the math regs will be loaded > > back into regs. > > It looks to me that you are loading up the math regs on every vcpu > load, not just those with an active transaction. That seems like > overkill. > > > If there is a FP/VEC/VSX unavailable exception during transaction active > > state, the math checkpoint content might be incorrect and we need to do > > treclaim./load the correct checkpoint val/trechkpt. sequence to retry the > > transaction. > > I would prefer a simpler approach where just before entering the > guest, we check if the guest MSR TM bit is set, and if so we make sure > that whichever math regs are enabled in the guest MSR are actually > loaded on the CPU, that is, that guest_owned_ext has the same bits set > as the guest MSR. Then we never have to handle a FP/VEC/VSX > unavailable interrupt with a transaction active (other than by simply > passing it on to the guest). Good idea. I will rework as this way. Thanks, - Simon
