Per Processor Programming Reference, CPUID_Fn80000005_EDX should report L1 instruction cache associativity as 4(way) instead of 2(way). Signed-off-by: Babu Moger <babu.moger@xxxxxxx> --- target/i386/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3818d72831..cb055f5940 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -123,7 +123,7 @@ /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ #define L1I_LINES_PER_TAG 1 #define L1I_SIZE_KB_AMD 64 -#define L1I_ASSOCIATIVITY_AMD 2 +#define L1I_ASSOCIATIVITY_AMD 4 /* Level 2 unified cache: */ #define L2_LINE_SIZE 64 -- 2.16.0
