The POWER9 "Nimbus" v2.2 (referred to as DD2.2) chip has some hardware
bugs fixed that were present in earlier versions, and contains new
workarounds for other hardware bugs.
POWER9 DD2.2 can run with some threads of a core in hashed page table
(HPT) MMU mode while other threads are in radix MMU mode.
Patches 2 and 3 of this series adjust the guest entry/exit code
so that we don't do the (expensive) inter-thread synchronization
introduced in commit c01015091a77 ("KVM: PPC: Book3S HV: Run HPT
guests on POWER9 radix hosts", 2017-10-19) when running a HPT
guest on a radix host, and we don't require the host to be in
SMT1 mode with indep_threads_mode=N. This means that guests can be
run in the normal fashion without any special host configuration
regardless of whether they will want to use the HPT or radix MMU mode.
POWER9 DD2.2 contains features which are intended to allow
hypervisor software to work around deficiencies in the handling
of transactional memory suspended mode which are present in DD2.2 and
all previous versions. This involves generating softpatch interrupts
and hypervisor maintenance interrupts on execution of certain
TM-related instructions, so that the hypervisor can store the
checkpointed CPU state in memory and emulate some of the TM state
transitions. With this, we can allow guests to use transactional
memory facilities even if the host kernel does not allow host
userspace programs to use TM. This makes it possible to migrate
guests from a POWER8 system to a POWER9. Since KVM on POWER8 makes TM
available to guests, any guest on a POWER8 may be using TM, and
therefore to be able to migrate such a guest to POWER9 we have to be
able to provide TM facilities to it.
Patch 1 is a bug-fix, relevant on POWER9 systems, to make sure we
don't enter the guest without the XIVE context loaded.
Paul.
