Thanks, Jim. Highly appreciated. Jim Mattson <jmattson@xxxxxxxxxx> wrote: > Nadav, > > See section 2.5.1.2 (paragraph 3) in > https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf. > > On Tue, Jan 9, 2018 at 9:03 PM, Nadav Amit <nadav.amit@xxxxxxxxx> wrote: >> Paolo Bonzini <pbonzini@xxxxxxxxxx> wrote: >> >>> On 09/01/2018 17:48, Liran Alon wrote: >>>>>> + if (have_spec_ctrl) { >>>>>> + rdmsrl(MSR_IA32_SPEC_CTRL, vmx->spec_ctrl); >>>>>> + if (vmx->spec_ctrl != 0) >>>>>> + wrmsrl(MSR_IA32_SPEC_CTRL, 0); >>>> >>>> As I said also on the AMD patch, I think this is a bug. >>>> Intel specify that we should set IBRS bit even if it was already set on every #VMExit. >>> >>> That's correct (though I'd like to understand _why_---I'm not inclined >>> to blindly trust a spec), but for now it's saving a wrmsr of 0. That is >>> quite obviously okay, and will be also okay after the bare-metal IBRS >>> patches. >>> >>> Of course the code will become something like >>> >>> if (using_ibrs || vmx->spec_ctrl != 0) >>> wrmsrl(MSR_IA32_SPEC_CTRL, host_ibrs); >>> >>> optimizing the case where the host is using retpolines. >> >> Excuse my ignorance: Can you point me to the specifications that mention “we >> should set IBRS bit even if it was already set on every #VMExit” ? >> >> Thanks, >> Nadav
