It's unclear from Intel's documentation whether writing bit 0 of IA32_SPEC_CTRL or bit 0 of IA32_PRED_CMD will flush the BHB. (At least, it's unclear from the documentation I have.) The retpoline patches include code for *filling* the RSB, but if you invoke the RSB refill code from kernel text before VM-entry, you still reveal information about KASLR to the guest. I think we may need a copy of the RSB refill code on a dynamically allocated page. In fact, we may need ~32 branches on that page to clobber the BHB. That means that maybe we can't do VM-entry from kernel text (unless one of IBRS or IBPB flushes the BHB). On Tue, Jan 9, 2018 at 1:42 PM, Paolo Bonzini <pbonzini@xxxxxxxxxx> wrote: > On 09/01/2018 21:57, Jim Mattson wrote: >> Before VM-entry, don't we need to flush the BHB and the RSB to avoid >> revealing KASLR information to the guest? (Thanks to Liran for >> pointing this out.) > > I don't know how you flush the BHB? As to the RSB, that would also be > part of generic Linux code so I've not included it yet in this series > which was mostly about the new MSRs and CPUID bits. > > Paolo
