This series adds emulation for some transactional memory instructions that will be used on POWER9 DD2.2 processors as part of the workarounds for hardware bugs. The basic idea is that because the CPU hardware cannot maintain a full checkpoint of the architected state for all four threads, it needs to be able to escape from suspended state at times. (The CPU can escape from transactional state simply by aborting the transaction and rolling back, but in suspended state it can't roll back until the transaction is resumed.) This is implemented by having a "fake suspend" state where the MSR indicates suspended state but there is no checkpoint. This is differentiated from real suspended state by a new bit in the PSSCR register. In addition to these two patches, there will need to be another patch which handles HMIs (hypervisor maintenance interrupts) which the hardware will generate on threads that are in real suspend state at the point where another thread that was in a stop instruction wants to wake up. The process of taking the HMI and exiting the guest to host context will do a treclaim which will eliminate the checkpointed state from the CPU hardware, so the only thing remaining will be to clear the HMER bit that indicates the cause of the HMI. The series is against v4.14. Paul.
