On Mon, Nov 06, 2017 at 11:44:24AM -0600, Janakarajan Natarajan wrote:
> Add the EventSelect and Counter MSRs for AMD Core Perf Extension.
>
> Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@xxxxxxx>
> ---
> arch/x86/include/asm/msr-index.h | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index 17f5c12..1dcbd29 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -337,7 +337,21 @@
>
> /* Fam 15h MSRs */
> #define MSR_F15H_PERF_CTL 0xc0010200
> +#define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL
> +#define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2)
> +#define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4)
> +#define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6)
> +#define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8)
> +#define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10)
> +
> #define MSR_F15H_PERF_CTR 0xc0010201
> +#define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR
> +#define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2)
> +#define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4)
> +#define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6)
> +#define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8)
> +#define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10)
> +
> #define MSR_F15H_NB_PERF_CTL 0xc0010240
> #define MSR_F15H_NB_PERF_CTR 0xc0010241
> #define MSR_F15H_PTSC 0xc0010280
> --
Reviewed-by: Borislav Petkov <bp@xxxxxxx>
--
Regards/Gruss,
Boris.
SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nürnberg)
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