On Wed, 8 Nov 2017, Haozhong Zhang wrote: > On 11/03/17 10:15 -0400, Mikulas Patocka wrote: > > > > > > On Tue, 31 Oct 2017, Haozhong Zhang wrote: > > > > > [I just copy the commit message from patch 2] > > > > > > Some reserved pages, such as those from NVDIMM DAX devices, are > > > not for MMIO, and can be mapped with cached memory type for better > > > performance. However, the above check misconceives those pages as > > > > Note that cached memory type on persistent memory has horrible > > performance. The clwb instruction on Broadwell is very slow - when you > > write to persistent memory and use clwb to flush cache, the performance is > > about 350MB/s. > > Wasn't clwb first introduced on Skylake? > > Haozhong You're right - the clwb() function uses clflushopt on Broadwell - that's what I meant is slow. Mikulas
