2017-11-05 21:52 GMT+08:00 Nikita Leshenko <nikita.leshchenko@xxxxxxxxxx>:
> Avoid firing a level-triggered interrupt that has the Remote IRR bit set,
> because that means that some CPU is already processing it. The Remote
> IRR bit will be cleared after an EOI and the interrupt will refire
> if the irq line is still asserted.
>
> This behavior is aligned with QEMU's IOAPIC implementation that was
> introduced by commit f99b86b94987
> ("x86: ioapic: ignore level irq during processing") in QEMU.
>
> Signed-off-by: Nikita Leshenko <nikita.leshchenko@xxxxxxxxxx>
> Reviewed-by: Liran Alon <liran.alon@xxxxxxxxxx>
> Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@xxxxxxxxxx>
Reviewed-by: Wanpeng Li <wanpeng.li@xxxxxxxxxxx>
> ---
> arch/x86/kvm/ioapic.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/kvm/ioapic.c b/arch/x86/kvm/ioapic.c
> index ae0a7dc318b2..5c9231139243 100644
> --- a/arch/x86/kvm/ioapic.c
> +++ b/arch/x86/kvm/ioapic.c
> @@ -323,7 +323,9 @@ static int ioapic_service(struct kvm_ioapic *ioapic, int irq, bool line_status)
> struct kvm_lapic_irq irqe;
> int ret;
>
> - if (entry->fields.mask)
> + if (entry->fields.mask ||
> + (entry->fields.trig_mode == IOAPIC_LEVEL_TRIG &&
> + entry->fields.remote_irr))
> return -1;
>
> ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
> --
> 2.13.3
>
