On 16 October 2017 at 10:26, Christoffer Dall <cdall@xxxxxxxxxx> wrote: > Hi Eric, > > On Mon, Sep 25, 2017 at 03:34:36PM +0200, Eric Auger wrote: >> When the GITS_BASER<n>.Valid gets cleared, the data structures in >> guest RAM are not provisionned anymore. The device, collection >> and LPI lists stored in the in-kernel ITS represent the same >> information in some form of cache. So let's void the cache. > > Just a thought. What about the opposite case, if the BASERs were > previously not valid, and then become valid, is the ITS expected restore > the state from memory? Architecturally speaking, it's a cache. As soon as the guest turns the GITS_CTLR.Enabled bit on, the ITS is permitted to start reading from the tables. It's an implementation choice whether it wants to preload a bunch of stuff, only load it up when it becomes necessary or even leave it all in memory and cache nothing. Eric wrote: > Also the spec does not mandate clearing the cache when BASER > moves to invalid (which this patch does), although this would > have made sense to me. The spec says that messing with GITS_BASER while GITS_CTRL.Enabled is set or GITS_CTLR.Quiescent is 0 is UNPREDICTABLE. And it says that once the OS has done the Enabled/Quiescent handshake then the ITS must have written out any dirty data to memory and stopped doing anything. So the effect is that BASER can't ever move to invalid while the caches are dirty. thanks -- PMM
